SN74LVC2G02 - Dual 2-Input Positive-NOR Gate

This dual 2-input positive-NOR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G02 performs the Boolean function Y = A + B or Y = A • B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LVC2G02" keyword are: SN74LVC2G02DCT3 , SN74LVC2G02DCTR , SN74LVC2G02DCTR , SN74LVC2G02DCTR , MMSZ6V , SN74LVC2G02DCTRE4 , SN74LVC2G02DCTRE4 , SN74LVC2G02DCTRG4 , SN74LVC2G02DCTRG4 , SN74LVC2G02DCUR , SN74LVC2G02DCUR , SN74LVC2G02DCURE4 , SN74LVC2G02DCURG4 , SN74LVC2G02DCURG4/C02R , SN74LVC2G02DCUT , SN74LVC2G02DCUT , SN74LVC2G02DCUTE4 , SN74LVC2G02DCUTE4 , SN74LVC2G02MDCUREP , SN74LVC2G02MDCUREP , SN74LVC2G02YEAR

• Available in the Texas Instruments NanoFree Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.9 ns at 3.3 V
• Low Power Consumption, 10-μA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 1000-V Charged-Device Model (C101)