SN74LVC1G32 - Single 2-Input Positive-OR Gate

Updated : 2020-01-09 14:37:18
Description

This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G32 device performs the Boolean function Y = A + B or Y = A\ + B\ in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G32 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 × 0.8 mm.

Products containing the "SN74LVC1G32" keyword are: SN74LVC1G3208DBVR , SN74LVC1G3208DBVR , SN74LVC1G3208DBVRG4 , SN74LVC1G3208DBVT , SN74LVC1G3208DBVT , SN74LVC1G3208DBVT(HBM2K, , SN74LVC1G3208DCKR , SN74LVC1G3208DCKR , SN74LVC1G3208DCKRG4 , SN74LVC1G3208DCKT , SN74LVC1G3208DCKT , SN74LVC1G3208YZPR , SN74LVC1G3208YZPR , SN74LVC1G3208YZTR , SN74LVC1G3208YZTR , SN74LVC1G32DBVR , SN74LVC1G32DBVR , SN74LVC1G32DBVR3 , SN74LVC1G32DBVRE4 , SN74LVC1G32DBVRE4
Features

  • Available in the Ultra-Small 0.64 mm2
    Package (DPW) with 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5-V
  • Supports Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3-V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3-V
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics
StatusACTIVE
SubFamilyOR gate
Technology FamilyLVC
VCC5.5
Channels1
Inputs per channel2
ICC @ nom voltage0.01
IOL32
IOH-32
Input typeStandard CMOS
Output typePush-Pull
FeaturesPartial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Ultra High Speed (tpd <5ns)
Data rate100
RatingCatalog
Operating temperature range-40 to 125
Package GroupDSBGA|5
Package size: mm2:W x L (PKG)See datasheet (DSBGA)
Approx. price0.07 | 1ku