SN74LV11A - Triple 3-Input Positive-AND Gates

These triple 3-input positive-AND gates are designed for 2-V to 5.5-V V_CC operation.

The ’LV11A devices perform the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Products containing the "SN74LV11A" keyword are: SN74LV11AD , SN74LV11AD , SN74LV11ADB , SN74LV11ADBR , SN74LV11ADBR , SN74LV11ADBRG4 , SN74LV11ADG4 , SN74LV11ADG4 , SN74LV11ADGVR , SN74LV11ADGVR , SN74LV11ADGVRE4 , SN74LV11ADR , SN74LV11ADR , SN74LV11ADRG4 , SN74LV11ANSR , SN74LV11ANSR , SN74LV11ANSRG4 , SN74LV11APW , SN74LV11APW , SN74LV11APWE4

• 2-V to 5.5-V V_CC Operation
• Max t_pd of 7 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
     >2.3 V at V_CC = 3.3 V, T_A = 25°C
• Support Mixed-Mode Voltage Operation on All Ports
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)