SN74AUC1G00 - Single 2-Input Positive-NAND Gate

This single 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.

Products containing the "SN74AUC1G00" keyword are: SN74AUC1G00DBVR , SN74AUC1G00DBVR , SN74AUC1G00DBVRG4 , SN74AUC1G00DCKR , SN74AUC1G00DCKR , SN74AUC1G00DCKRE4 , SN74AUC1G00DCKRE4 , SN74AUC1G00DCKRG4 , SN74AUC1G00DCKRG4 , SN74AUC1G00DRLR , SN74AUC1G00DRLR , SN74AUC1G00DRLRG4 , SN74AUC1G00YEPR , SN74AUC1G00YZAR , SN74AUC1G00YZPR , SN74AUC1G00YZPR

• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial-Power-Down Mode Operation
• Sub 1-V Operable
• Max t_pd of 2.2 ns at 1.8 V
• Low Power Consumption, 10-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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