SN74LVC2G86 - Dual 2-Input Exclusive-Or Gate

This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

Products containing the "SN74LVC2G86" keyword are: SN74LVC2G86DCTR , SN74LVC2G86DCTR , SN74LVC2G86DCTRG4 , SN74LVC2G86DCTRG4 , SN74LVC2G86DCUR , SN74LVC2G86DCUR , SN74LVC2G86DCURE4 , SN74LVC2G86DCURG4 , SN74LVC2G86DCURG4 , SN74LVC2G86DCUT , SN74LVC2G86DCUT , SN74LVC2G86DCUTG4 , SN74LVC2G86YEAR , SN74LVC2G86YEPR , SN74LVC2G86YZAR , SN74LVC2G86YZPR , SN74LVC2G86YZPR

• Available in the Texas Instruments NanoFree Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.7 ns at 3.3 V
• Low Power Consumption, 10-μA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down Mode and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)