SN74LV27A - Triple 3-Input Positive-NOR Gate

Updated : 2020-01-09 14:37:20
Description

These triple 3-input positive-nor gates are designed for 2-V to 5.5-V VCC operation.

The 'LV27A devices perform the Boolean function Y = (A + B + C)\ or Y = A\ • B\ • C\ in positive logic.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Products containing the "SN74LV27A" keyword are: SN74LV27AD , SN74LV27AD , SN74LV27ADB , SN74LV27ADBR , SN74LV27ADBR , SN74LV27ADBRG4 , SN74LV27ADG4 , SN74LV27ADG4 , SN74LV27ADGVR , SN74LV27ADGVR , SN74LV27ADGVRG4 , SN74LV27ADR , SN74LV27ADR , SN74LV27ADRG4 , SN74LV27ANSR , SN74LV27ANSR , SN74LV27ANSRG4 , SN74LV27APW , SN74LV27APW , SN74LV27APWE4
Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 7 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
        <0.8 V at VCC, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
        >2.3 V at VCC, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics
StatusACTIVE
SubFamilyNOR gate
Technology FamilyLV-A
VCC5.5
Channels3
Inputs per channel3
ICC @ nom voltage0.02
IOL12
IOH-12
Input typeStandard CMOS
Output typePush-Pull
FeaturesPartial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Very High Speed (tpd 5-10ns)
Data rate70
RatingCatalog
Operating temperature range-40 to 85
Package GroupSOIC|14
Package size: mm2:W x L (PKG)[pf]14SO[/pf]: 80 mm2: 7.8 x 10.2 (SO|14)
Approx. price0.18 | 1ku