SN74LV10A - Triple 3-Input Positive-NAND Gate

Updated : 2020-01-09 14:37:19

Description

These triple 3-input positive-NAND gates are \designed for 2-V to 5.5-V V_CC operation.

The 'LV10A devices perform the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic.

These devices are fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Products containing the "SN74LV10A" keyword are: SN74LV10AD , SN74LV10AD , SN74LV10ADBR , SN74LV10ADBR , SN74LV10ADBRG4 , SN74LV10ADBRG4 , SN74LV10ADGVR , SN74LV10ADGVR , SN74LV10ADGVRE4 , SN74LV10ADGVRG4 , SN74LV10ADGVRG4 , SN74LV10ADR , SN74LV10ADR , SN74LV10ADRG4 , SN74LV10ADRG4 , SN74LV10ANSR , SN74LV10ANSR , SN74LV10APW , SN74LV10APW , SN74LV10APWE4

Features

2-V to 5.5-V V_CC Operation
Max t_pd of 7 na at 5 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2.3 V at V_CC, T_A = 25°C
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Parametrics

Status	ACTIVE
SubFamily	NAND gate
Technology Family	LV-A
VCC	5.5
Channels	3
Inputs per channel	3
ICC @ nom voltage	0.02
IOL	12
IOH	-12
Input type	Standard CMOS
Output type	Push-Pull
Features	Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Very High Speed (tpd 5-10ns)
Data rate	70
Rating	Catalog
Operating temperature range	-40 to 85
Package Group	SOIC\|14
Package size: mm2:W x L (PKG)	[pf]14SO[/pf]: 80 mm2: 7.8 x 10.2 (SO\|14)
Approx. price	0.07 \| 1ku