SN74ABT240A - Octal Buffers/Drivers With 3-State Outputs

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs.

The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Products containing the "SN74ABT240A" keyword are: SN74ABT240ADB , SN74ABT240ADB(AB240A) , SN74ABT240ADB/AB240A , SN74ABT240ADBLE , SN74ABT240ADBR , SN74ABT240ADBR AB240A , SN74ABT240ADBRG4 , SN74ABT240ADBRG4 , SN74ABT240ADW , SN74ABT240ADW , SN74ABT240ADWG4 , SN74ABT240ADWG4 , SN74ABT240ADWR , SN74ABT240ADWR , SN74ABT240ADWRG4 , SN74ABT240ADWRG4 , SN74ABT240AN , SN74ABT240AN , SN74ABT240ANS , SN74ABT240ANSR

• Typical V_OLP (Output Ground Bounce)
     <1 V at V_CC = 5 V, T_A = 25°C
• High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)