SN74ABT162827A - 20-Bit Buffers/Drivers With 3-State Outputs

The ’ABT162827A devices are noninverting 20-bit buffers composed of two 10-bit buffers with separate output-enable signals. For either 10-bit buffer, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer are in the high-impedance state.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE\ shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Products containing the "SN74ABT162827A" keyword are: SN74ABT162827ADGGR , SN74ABT162827ADGGR , SN74ABT162827ADGGRG4 , SN74ABT162827ADL , SN74ABT162827ADL , SN74ABT162827ADLR , SN74ABT162827ADLR

• Members of the Texas Instruments Widebus™ Family
• Output Ports Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• High-Impedance State During Power Up and Power Down
• Typical V_OLP (Output Ground Bounce)
      < 1 V at V_CC= 5 V, T_A = 25°C
• Distributed V_CC and GND Pin Minimizes High-Speed Switching Noise
• I_off and Power-Up 3-State Support Hot Insertion
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

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