SN74ABT540 - Octal Buffers/Drivers With 3-State Outputs

The ’ABT540 octal buffers and line drivers are ideal for driving bus lines or buffer memory address registers. The devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT540 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT540 is characterized for operation from -40°C to 85°C.

Products containing the "SN74ABT540" keyword are: SN74ABT5400ADW , SN74ABT5400ADWE4 , SN74ABT5400ADWE4 , SN74ABT5400ADWG4 , SN74ABT5400ADWR , SN74ABT5401DW , SN74ABT5401DWE4 , SN74ABT5401DWR , SN74ABT5401DWRE4 , SN74ABT5401DWRG4 , SN74ABT5402ADW , SN74ABT5402ADW , SN74ABT5402ADWG4 , SN74ABT5402ADWR , SN74ABT5402ADWR , SN74ABT5402DW , SN74ABT5403DW , SN74ABT5403DWE4 , SN74ABT5403DWG4 , SN74ABT5403DWR

• State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package

EPIC-IIB is a trademark of Texas Instruments Incorporated.