SN74ABT541B - Octal Buffers/Drivers With 3-State Outputs

The SN54ABT541 and SN74ABT541B octal buffers and line drivers are ideal for driving bus lines or buffering memory address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.

The 3-state control gate is a two-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT541 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT541B is characterized for operation from -40°C to 85°C.

Products containing the "SN74ABT541B" keyword are: SN74ABT541B , SN74ABT541BDB , SN74ABT541BDBG4 , SN74ABT541BDBLE , SN74ABT541BDBR , SN74ABT541BDBR , SN74ABT541BDBR AB541B , SN74ABT541BDBRE4 , SN74ABT541BDBRE4 , SN74ABT541BDBRG4 , SN74ABT541BDBRG4 , SN74ABT541BDW , SN74ABT541BDW , SN74ABT541BDWG4 , SN74ABT541BDWR , SN74ABT541BDWR , SN74ABT541BDWR/7.2 , SN74ABT541BDWRE4 , SN74ABT541BDWRE4 , SN74ABT541BDWRG4

• State-of-the-Art EPIC-IIB™ BiCMOS DesignSignificantly Reduces Power Dissipation
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Impedance State During Power Up and Power Down
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (N) and Ceramic (J) DIPs

EPIC-IIB is a trademark of Texas Instruments.