SN74ABT827 - 10-Bit Buffers/Drivers With 3-State Outputs

These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity.

The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all ten outputs are in the high-impedance state. The 'ABT827 provide true data at the outputs.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT827 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT827 is characterized for operation from -40°C to 85°C.

Products containing the "SN74ABT827" keyword are: SN74ABT827DBR , SN74ABT827DBR , SN74ABT827DBR AB827 , SN74ABT827DBRG4 , SN74ABT827DW , SN74ABT827DW , SN74ABT827DWR , SN74ABT827DWR , SN74ABT827NSR , SN74ABT827NT , SN74ABT827NTE4 , SN74ABT827PW , SN74ABT827PW , SN74ABT827PWG4 , SN74ABT827PWG4 , SN74ABT827PWR , SN74ABT827PWR , SN74ABT827PWRG4

• State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Impedance State During Power Up and Power Down
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

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