These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The ACT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When (OE)\ is low, the device passes inverted data from the A inputs to the Y outputs. When (OE)\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Products containing the "SN74ACT240" keyword are: SN74ACT240DBR , SN74ACT240DBR , SN74ACT240DBR AD240 , SN74ACT240DBRG4 , SN74ACT240DW , SN74ACT240DW , SN74ACT240DWE4 , SN74ACT240DWE4 , SN74ACT240DWG4 , SN74ACT240DWG4 , SN74ACT240DWR , SN74ACT240DWR , SN74ACT240DWR SOP7.2 , SN74ACT240DWRE4 , SN74ACT240DWRE4 , SN74ACT240DWRG4 , SN74ACT240N , SN74ACT240N , SN74ACT240NE4 , SN74ACT240NS| Status | ACTIVE |
| SubFamily | Inverting buffer/driver |
| Technology Family | ACT |
| VCC | 5.5 |
| Bits | 8 |
| Voltage | 5 |
| F @ nom voltage | 90 |
| tpd @ Nom Voltage | 9.5 |
| ICC @ nom voltage | 0.04 |
| IOL | 24 |
| IOH | -24 |
| Rating | Catalog |
| Operating temperature range | -40 to 85 |
| Package Group | PDIP|20 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.18 | 1ku |