SN74AUP1G00 - Low-Power Single Two-Input Positive-NAND Gate

This single 2-input positive-NAND gate performs the Boolean function Y = A × B or Y = A + B in positive logic.

• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)
• Available in the Ultra Small 0.64 mm² Package (DPW) with 0.5-mm Pitch
• Low Static-Power Consumption (I_CC = 0.9 µA Max)
• Low Dynamic-Power Consumption (C_pd = 4 pF Typical at 3.3 V)
• Low Input Capacitance (C_i = 1.5 pF Typical)
• Low Noise Overshoot and Undershoot <10% of V_CC
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (V_hys = 250 mV Typical at 3.3 V)
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t_pd = 4.8 ns Maximum at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II