SN74LVC1G0832 - Single 3-Input Positive AND-OR Gate

This device is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.

By tying one input to GND or V_CC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to V_CC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to V_CC (Y = A + C).

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LVC1G0832" keyword are: SN74LVC1G0832DBVR , SN74LVC1G0832DBVR , SN74LVC1G0832DBVRG4 , SN74LVC1G0832DBVT , SN74LVC1G0832DBVT , SN74LVC1G0832DCKR , SN74LVC1G0832DCKR , SN74LVC1G0832DCKT , SN74LVC1G0832DCKT , SN74LVC1G0832YZPR , SN74LVC1G0832YZPR

• Available in the Texas Instruments NanoFree Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to V_CC
• Max t_pd of 5 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Input Hysteresis Allows Slow Input
  Transition and Better Switching Noise
  Immunity at the Input
  (V_hys = 250 mV Typ @ 3.3 V)
• Can Be Used in Three Combinations:
  • AND-OR Gate
  • AND Gate
  • OR Gate
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)