SN74LVC2G132 - Dual 2-Input NAND Gate with Schmitt-Trigger Inputs

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (V_T+) and negative-going (V_T-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LVC2G132" keyword are: SN74LVC2G132DCTR , SN74LVC2G132DCTR , SN74LVC2G132DCTRG4 , SN74LVC2G132DCTRTI , SN74LVC2G132DCUR , SN74LVC2G132DCUR , SN74LVC2G132DCURG4 , SN74LVC2G132DCUT , SN74LVC2G132DCUT , SN74LVC2G132YEPR , SN74LVC2G132YZPR , SN74LVC2G132YZPR

• Available in Texas Instruments NanoFree Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 5.3 ns at 3.3 V
• Low Power Consumption, 10-μA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
• Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)