SN74AUP1G99 - Low-Power Ultra-Configurable Multiple-Function Gate with 3-State Outputs

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2).

The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the input-disable feature, which allows floating input signals. The inputs and output are disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to V_CC or GND.

This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching noise immunity at the input.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUP1G99" keyword are: SN74AUP1G99DCTR , SN74AUP1G99DCTR , SN74AUP1G99DCTT , SN74AUP1G99DCTT , SN74AUP1G99DCUR , SN74AUP1G99DCUR , SN74AUP1G99DCURE4 , SN74AUP1G99DCURG4 , SN74AUP1G99DCUT , SN74AUP1G99DCUT , SN74AUP1G99DCUTE4 , SN74AUP1G99DCUTE4 , SN74AUP1G99DCUTG4 , SN74AUP1G99DCUTG4 , SN74AUP1G99YZPR , SN74AUP1G99YZPR

• Available in the Texas Instruments
  NanoFree™ Package
• Low Static-Power Consumption
  (I_CC = 0.9 µA Max)
• Low Dynamic-Power Consumption
  (C_pd = 5 pF Typ at 3.3 V)
• Low Input Capacitance (C_I = 1.5 pF)
• Low Noise – Overshoot and Undershoot
  <10% of V_CC
• Input-Disable Feature Allows Floating Input Conditions
• I_off Supports Partial-Power-Down Mode Operation
• Includes Schmitt-Trigger Inputs
• Wide Operating V_CC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• t_pd = 7.4 ns Max at 3.3 V
• Suitable for Point-to-Point Applications
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model
    (A114-B, Class II)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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