This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G08-Q1 performs the Boolean function Y = A B or Y = A\ + B\ in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Status | ACTIVE |
SubFamily | AND gate |
Technology Family | LVC |
VCC | 5.5 |
Channels | 2 |
Inputs per channel | 2 |
ICC @ nom voltage | 0.01 |
IOL | 32 |
IOH | -32 |
Input type | Standard CMOS |
Output type | Push-Pull |
Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Ultra High Speed (tpd <5ns) |
Data rate | 100 |
Rating | Automotive |
Operating temperature range | -40 to 85 |
Package Group | SM8|8 |
Package size: mm2:W x L (PKG) | [pf]8SM8[/pf]: 12 mm2: 4 x 2.95 (SM8|8) |
Approx. price | 0.22 | 1ku |