This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G32 performs the Boolean function Y = A + B or Y = A\ B\ in positive logic.
This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Status | ACTIVE |
SubFamily | OR gate |
Technology Family | LVC |
VCC | 5.5 |
Channels | 1 |
Inputs per channel | 2 |
ICC @ nom voltage | 0.01 |
IOL | 32 |
IOH | -32 |
Input type | Standard CMOS |
Output type | Push-Pull |
Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Ultra High Speed (tpd <5ns) |
Data rate | 100 |
Rating | HiRel Enhanced Product |
Operating temperature range | -40 to 85 |
Package Group | SC70|5 |
Package size: mm2:W x L (PKG) | [pf]5SC70[/pf]: 4 mm2: 2.1 x 2 (SC70|5) |
Approx. price | 0.13 | 1ku |