The SN74AUP1G57 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND, NOR, XNOR, inverter, and noninverter. All inputs can be connected to VCC or GND.
Products containing the "SN74AUP1G57" keyword are: SN74AUP1G57DBVR , SN74AUP1G57DBVR , SN74AUP1G57DBVRG4 , SN74AUP1G57DBVT , SN74AUP1G57DBVT , SN74AUP1G57DCKR , SN74AUP1G57DCKR , SN74AUP1G57DCKRE4 , SN74AUP1G57DCKRE4 , SN74AUP1G57DCKRG4 , SN74AUP1G57DCKRG4 , SN74AUP1G57DCKT , SN74AUP1G57DCKT , SN74AUP1G57DRLR , SN74AUP1G57DRLR , SN74AUP1G57DRLR/HHR , SN74AUP1G57DRLRG4 , SN74AUP1G57DRLRG4 , SN74AUP1G57DRYR , SN74AUP1G57DRYRAll other trademarks are the property of their respective owners
Status | ACTIVE |
SubFamily | Configurable gate |
Technology Family | AUP |
VCC | 3.6 |
Channels | 1 |
Inputs per channel | 1 |
ICC @ nom voltage | 0.0009 |
IOL | 4 |
IOH | -4 |
Input type | Standard CMOS |
Output type | Push-Pull |
Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Very High Speed (tpd 5-10ns) |
Data rate | 100 |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | DSBGA|6 |
Package size: mm2:W x L (PKG) | See datasheet (DSBGA) |
Approx. price | 0.09 | 1ku |