SN65LVDS104 - 1:4 LVDS Clock Fanout Buffer

The SN65LVDS10x are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

The SN65LVDS10x are characterized for operation from –40°C to 85°C.

The SN65LVDS10x are members of a family of LVDS repeaters. A brief overview of the family is provided in the Selection Guide to LVDS Repeaters section.

• Receiver and Drivers Meet or Exceed the
  Requirements of ANSI EIA/TIA-644 Standard
  • SN65LVDS105 Receives Low-Voltage TTL
    (LVTTL) Levels
  • SN65LVDS104 Receives Differential Input
    Levels, ±100 mV
• Typical Data Signaling Rates to 400 Mbps or
  Clock Frequencies to 400 MHz
• Operates From a Single 3.3-V Supply
• Low-Voltage Differential Signaling With Typical
  Output Voltage of 350 mV and a 100-Ω Load
• Propagation Delay Time
  • SN65LVDS105 – 2.2 ns (Typ)
  • SN65LVDS104 – 3.1 ns (Typ)
• LVTTL Levels Are 5-V Tolerant
• Electrically Compatible With LVDS, PECL,
  LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
  SSTL, or HSTL Outputs With External Networks
• Driver Outputs Are High-Impedance When
  Disabled or With V_CC <1.5 V
• Bus-Pin ESD Protection Exceeds 16 kV
• SOIC and TSSOP Packaging