SN65LVEP11 - PECL/ECL 1:2 Fanout Buffer

The SN65LVEP11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain known logic levels when the inputs are in an open condition. Single-ended clock input operation is limited to V_CC ≥ 3 V in PECL mode, or V_EE ≤ 3 V in NECL mode. The device is housed in an industry-standard SOIC-8 package and is also available in TSSOP-8 package option.

• 1:2 PECL/ECL Fanout Buffer
• Operating Range
  • PECL: V_CC = 2.375 V to 3.8V With V_EE = 0 V
  • NECL: V_CC = 0 V With V_EE = -2.375V to
    -3.8 V
• Open Input Default State
• Support for Clock Frequencies > 3.0 GHz
• 240 ps Typical Propagation Delay
• Deterministic Output Value for Open Input Conditions
• Q Output Will Default Low When Input Open or at V_EE
• Built-in Temperature Compensation
• Drop in Compatible to MC10LVEP11, MC100LVEP11
• LVDS Input Compatible