TLC2933A - Phase Locked Loop

Updated : 2020-01-09 14:25:19
Description

The TLC2933A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage. The high speed PFD with internal charge pump detects the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions, which can be used as power-down mode. Due to the TLC2933A high speed and stable oscillation capability, the TLC2933A is suitable for use as a high-performance PLL.

Products containing the "TLC2933A" keyword are: TLC2933AIPW , TLC2933AIPW , TLC2933AIPWG4 , TLC2933AIPWG4 , TLC2933AIPWR , TLC2933AIPWR , TLC2933AIPWR-1 , TLC2933AIPWRG4 , TLC2933AIPWRG4
Features

  • VCO (Voltage-Controlled Oscillator):
    • Complete Oscillator Using Only One External Bias Resistor (RBIAS)
    • Lock Frequency:
      • 30 MHz to 55 MHz (VDD = 3 V ±5%, TA = -20°C to 75°C, x1 Output)
      • 30 MHz to 60 MHz (VDD = 3.3 V ±5%, TA = -20°C to 75°C, x1 Output)
      • 43 MHz to 110 MHz (VDD = 5 V ±5%, TA = -20°C to 75°C, x1 Output)
    • Selectable Output Frequency
  • PFD (Phase Frequency Detector): High Speed, Edge-Triggered Detector with Internal Charge Pump
  • Independent VCO, PFD Power-Down Mode
  • Thin Small-Outline Package (14 Terminal)
  • CMOS Technology
  • Pin Compatible TLC2933IPW

Parametrics
StatusNRND
SubFamilyZero delay buffers
Additive RMS jitter
Output frequency
Input level
Number of outputs2
Output level
VCC3.3^5
VCC out
Input frequency
Operating temperature range-20 to 75
Package GroupTSSOP|14
Package size: mm2:W x L (PKG)[pf]14TSSOP[/pf]: 32 mm2: 6.4 x 5 (TSSOP|14)
RatingCatalog
Approx. price1.74 | 1ku