SN65LVDS116 - 1:16 LVDS Clock Fanout Buffer
Updated : 2020-01-09 14:25:18Description
Products containing the "SN65LVDS116" keyword are: SN65LVDS116DGG , SN65LVDS116DGG , SN65LVDS116DGGG4 , SN65LVDS116DGGG4 , SN65LVDS116DGGR , SN65LVDS116DGGR , SN65LVDS116DGGRG4
Features
- One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
- Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
- Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of the Four Banks
- Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-
ParametricsStatus ACTIVE SubFamily Differential Additive RMS jitter N/A Output frequency 400 Input level LVDS Number of outputs 16 Output level LVDS VCC 3.3 VCC out 3.3 Input frequency 400 Operating temperature range -40 to 85 Package Group TSSOP|64 Package size: mm2:W x L (PKG) [pf]64TSSOP[/pf]: 138 mm2: 8.1 x 17 (TSSOP|64) Rating Catalog Approx. price 5.18 | 1ku Similar products- LMK04906 - Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs
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