These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
Products containing the "SN74LVTH273" keyword are: SN74LVTH273DBR , SN74LVTH273DBR , SN74LVTH273DBRE4 , SN74LVTH273DBRE4 , SN74LVTH273DBRG , SN74LVTH273DBRG4 , SN74LVTH273DW , SN74LVTH273DW , SN74LVTH273DWG4 , SN74LVTH273DWR , SN74LVTH273DWR , SN74LVTH273DWR (PB) , SN74LVTH273DWRE4 , SN74LVTH273DWRE4 , SN74LVTH273DWRG4 , SN74LVTH273DWRG4 , SN74LVTH273IPWREP , SN74LVTH273IPWREP , SN74LVTH273MNSREP , SN74LVTH273MNSREPStatus | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | LVT |
VCC | 3.6 |
Bits | 8 |
Voltage | 3.3 |
F @ nom voltage | 160 |
ICC @ nom voltage | 5 |
tpd @ Nom Voltage | 4.9 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | SOIC|20 |
Package size: mm2:W x L (PKG) | [pf]20SO[/pf]: 98 mm2: 7.8 x 12.6 (SO|20) |
Approx. price | 0.26 | 1ku |