SN74LVC112A - Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

Updated : 2020-01-09 14:41:17
Description

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.

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Features

  • Operates From 1.65 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.8 ns at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 3000-V Human-Body Model
    • 200-V Machine Model
    • 1500-V Charged-Device Model

Parametrics
StatusACTIVE
SubFamilyJ-K flip-flop
Technology FamilyLVC
VCC3.6
Bits2
Voltage3.3
F @ nom voltage100
ICC @ nom voltage0.01
tpd @ Nom Voltage4.8
3-state output
RatingCatalog
Operating temperature range-40 to 125
Package GroupSOIC|16
Package size: mm2:W x L (PKG)[pf]16SO[/pf]: 80 mm2: 7.8 x 10.2 (SO|16)
Approx. price0.21 | 1ku
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