The \x92FCT377T devices have eight triggered D-type flip-flops with individual data (D) inputs. The common buffered clock (CP) inputs load all flip-flops simultaneously when the clock-enable (CE\) input is low. The register is fully edge triggered. The state of each D input at one setup time before the low-to-high clock transition is transferred to the corresponding flip-flop output (O). CE\ must be stable only one setup time prior to the low-to-high clock transition for predictable operation.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Products containing the "CY74FCT377T" keyword are: CY74FCT377TQCT , CY74FCT377TQCT , CY74FCT377TQCTE4 , CY74FCT377TQCTG4 , CY74FCT377TQCTG4Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | FCT |
VCC | 5.25 |
Bits | 8 |
Voltage | 5 |
F @ nom voltage | 70 |
ICC @ nom voltage | 0.2 |
tpd @ Nom Voltage | 7.2 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | SOIC|20 |
Package size: mm2:W x L (PKG) | [pf]20SOIC[/pf]: 132 mm2: 10.3 x 12.8 (SOIC|20) |
Approx. price | 0.26 | 1ku |