The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25- termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2573T can replace the CY74FCT573T to reduce noise in an existing design.
When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Products containing the "CY74FCT2573T" keyword are: CY74FCT2573TSOC , CY74FCT2573TSOC , CY74FCT2573TSOCE4 , CY74FCT2573TSOCG4 , CY74FCT2573TSOCT , CY74FCT2573TSOCT , CY74FCT2573TSOCTE4 , CY74FCT2573TSOCTG4Status | ACTIVE |
SubFamily | D-type latch |
Technology Family | FCT |
VCC | 5.25 |
Bits | 8 |
Voltage | 5 |
F @ nom voltage | 70 |
ICC @ nom voltage | 0.2 |
tpd @ Nom Voltage | 8 |
3-state output | Yes |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | SOIC|20 |
Package size: mm2:W x L (PKG) | [pf]20SOIC[/pf]: 132 mm2: 10.3 x 12.8 (SOIC|20) |
Approx. price | 0.35 | 1ku |