SN74LVC841A - 10-Bit Bus-Interface D-Type Latch With 3-State Outputs

This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V V_CC operation.

The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true data at its outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LVC841A" keyword are: SN74LVC841ADBR , SN74LVC841ADBR , SN74LVC841ADGVR , SN74LVC841ADGVR , SN74LVC841ADGVRG4 , SN74LVC841ADW , SN74LVC841ADW , SN74LVC841ADWR , SN74LVC841ADWRE4 , SN74LVC841ADWRG4 , SN74LVC841APW , SN74LVC841APW , SN74LVC841APWE4 , SN74LVC841APWG4 , SN74LVC841APWR , SN74LVC841APWR , SN74LVC841APWRG4 , SN74LVC841APWRG4 , SN74LVC841APWT

• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 6.7 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce)
     <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
     >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode Operation
• Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V V_CC)
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)