This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | FCT |
VCC | 5.25 |
Bits | 9 |
Voltage | 5 |
F @ nom voltage | 70 |
ICC @ nom voltage | 0.2 |
tpd @ Nom Voltage | 10 |
3-state output | Yes |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | SOIC|24 |
Package size: mm2:W x L (PKG) | [pf]24SOIC[/pf]: 160 mm2: 10.3 x 15.5 (SOIC|24) |
Approx. price | 0.31 | 1ku |