SN74LVC3G34 - Triple Buffer Gate

The SN74LVC3G34 device is a triple buffer gate designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC3G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LVC3G34" keyword are: SN74LVC3G34DCT3 , SN74LVC3G34DCTR , SN74LVC3G34DCTR , SN74LVC3G34DCTRE4 , SN74LVC3G34DCTRG4 , SN74LVC3G34DCTRG4 , SN74LVC3G34DCUR , SN74LVC3G34DCUR , SN74LVC3G34DCURE4 , SN74LVC3G34DCURG4 , SN74LVC3G34DCURG4 , SN74LVC3G34DCUT , SN74LVC3G34DCUT , SN74LVC3G34DCUTE4 , SN74LVC3G34DCUTG4 , SN74LVC3G34DCUTG4 , SN74LVC3G34YEAR , SN74LVC3G34YEAR , SN74LVC3G34YEPR , SN74LVC3G34YZAR

• Available in the Texas Instruments
  NanoFree Package
• Supports 5.5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.1 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the V_CC Level
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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