SN74LVC3G04 - Triple Inverter Gate

This triple inverter is designed for 1.65-V to 5.5-V V_CC operation. The SN74LVC3G04 device performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LVC3G04" keyword are: SN74LVC3G04DCT3 , SN74LVC3G04DCTR , SN74LVC3G04DCTR , SN74LVC3G04DCTR-1 , SN74LVC3G04DCTRE4 , SN74LVC3G04DCTRG4 , SN74LVC3G04DCTRG4 , SN74LVC3G04DCU3 , SN74LVC3G04DCU6 , SN74LVC3G04DCUR , SN74LVC3G04DCUR , SN74LVC3G04DCUR(LF) , SN74LVC3G04DCURE4 , SN74LVC3G04DCURG4 , SN74LVC3G04DCURG4 , SN74LVC3G04DCUT , SN74LVC3G04DCUT , SN74LVC3G04DCUTG4 , SN74LVC3G04YEAR , SN74LVC3G04YEPR

• Available in the Texas Instruments NanoFree Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.1 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
• Latch-Up Performance Exceeds 100 mA Per
  JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)