SN74LVC1G04 - Single Inverter

Updated : 2020-01-09 14:33:40
Description

This single inverter gate is designed for
1.65-V to 5.5-V VCC operation.

The SN74LVC1G04 device performs the Boolean function Y = A.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G04 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

Products containing the "SN74LVC1G04" keyword are: SN74LVC1G04DBRV , SN74LVC1G04DBVR , SN74LVC1G04DBVR , SN74LVC1G04DBVR(C04F) , SN74LVC1G04DBVR3 , SN74LVC1G04DBVRE4 , SN74LVC1G04DBVRE4 , SN74LVC1G04DBVRG4 , SN74LVC1G04DBVRG4 , SN74LVC1G04DBVT , SN74LVC1G04DBVT , SN74LVC1G04DBVT. , SN74LVC1G04DBVTE4 , SN74LVC1G04DBVTE4 , SN74LVC1G04DBVTG4 , SN74LVC1G04DBVTG4 , SN74LVC1G04DCK , SN74LVC1G04DCK3 , SN74LVC1G04DCKJ , SN74LVC1G04DCKR
Features

  • Available in the Ultra-Small 0.64-mm2
    Package (DPW) with 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages up to 5.5 V Allowing Down Translation to VCC
  • Max tpd of 3.3 ns at 3.3-V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3-V
  • Ioff Supports Live-Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)