SN74LVC2G125 - Dual Bus Buffer Gate with 3-State Outputs

The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-VV_CC operation. This device features dual line drivers with 3-state outputs.The outputs are disabled when the associated output-enable (OE) input ishigh.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

To ensure the high-impedance state during power up or power down,OE should be tied to V_CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of thedriver.

This device is fully specified for partial-power-down applications usingI_off. The I_off circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model
  • 1000-V Charged-Device Model
• Available in the Texas Instruments
  NanoFree™ Package
• Supports 5-V V_CC Operation
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.3 ns at 3.3 V
• Low Power Consumption, 10-µA Max I_CC
• ±24-mA Output Drive at 3.3 V
• Typical V_OLP (Output Ground Bounce)
  < 0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  > 2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down
  to the V_CC Level
• Latch-Up Performance Exceeds 100 mA Per
  JESD 78, Class II

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