SN74AUC1G125 - Single Bus Buffer Gate With 3-State Output

Updated : 2020-01-09 14:33:36
Description

This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but isdesigned specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC1G125 device is a single line driver with a 3-state output. The output isdisabled when the output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down,OE should be tied to VCC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of thedriver.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUC1G125" keyword are: SN74AUC1G125DBVR , SN74AUC1G125DBVR , SN74AUC1G125DBVRE4 , SN74AUC1G125DBVRG4 , SN74AUC1G125DCKR , SN74AUC1G125DCKR , SN74AUC1G125DCKRG4 , SN74AUC1G125YEAR , SN74AUC1G125YEPR , SN74AUC1G125YZAR , SN74AUC1G125YZPR , SN74AUC1G125YZPR , SN74AUC1G125YZTR , SN74AUC1G125YZTR
Features

  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial Power Down Mode and Back Drive Protection
  • Sub-1-V Operable
  • Max tpd of 2.5 ns at 1.8 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±8-mA Output Drive at 1.8 V

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