SN74ABT833 - 8-Bit to 9-Bit Parity Bus Transceivers

The 'ABT833 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error () output indicates whether or not an error in the B data has occurred. The output-enable ( and ) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT833 provide true data at their outputs.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the flag. is clocked into the register on the rising edge of the clock (CLK) input. The error flag register is cleared with a low pulse on the clear () input. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.

 

To ensure the high-impedance state during power up or power down, should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT833 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT833 is characterized for operation from -40°C to 85°C.

 

 

 

Products containing the "SN74ABT833" keyword are: SN74ABT833DW , SN74ABT833DW , SN74ABT833DWR , SN74ABT833DWRE4 , SN74ABT833DWRG4 , SN74ABT833NSR , SN74ABT833NSRE4 , SN74ABT833NSRG4 , SN74ABT833NT

• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Parity Error Flag With Parity Generator/Checker
• Register for Storage of the Parity Error Flag
• Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

 

EPIC-IIB is a trademark of Texas Instruments Incorporated.