SN74ABTH25245 - 25-Ohm Octal Bus Transceivers With 3-State Outputs

The 'ABTH25245 are 25- octal bus transceivers designed for asynchronous communication between data buses. They improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.

These devices allow noninverted data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can disable the device so that both buses are effectively isolated. When OE\ is low, the device is active.

These transceivers are capable of sinking 188 mA of I_OL current, which facilitates switching 25- transmission lines on the incident wave. The distributed V_CC and GND pins minimize switching noise for more-reliable system operation.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

When V_CC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABTH25245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABTH25245 is characterized for operation from -40°C to 85°C.

Products containing the "SN74ABTH25245" keyword are: SN74ABTH25245DW , SN74ABTH25245DW , SN74ABTH25245DWE4 , SN74ABTH25245DWE4 , SN74ABTH25245DWG4 , SN74ABTH25245DWR , SN74ABTH25245DWR , SN74ABTH25245NT , SN74ABTH25245NT

• State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Impedance State During Power Up and Power Down
• Designed to Facilitate Incident-Wave Switching for Line Impedances of 25 or Greater
• Distributed V_CC and GND Pin Configuration Minimizes High-Speed Switching Noise
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Package Options Include Plastic Small-Outline (DW) Package, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) DIPs

EPIC-IIB is a trademark of Texas Instruments Incorporated.