SN74ABT623 - Octal Bus Transceivers With 3-State Outputs

The SN54ABT623A and SN74ABT623 bus transceivers are designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing. The SN54ABT623A and SN74ABT623 provide true data at their outputs.

These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic levels at the output-enable (OEAB and OEBA\) inputs.

The output-enable inputs can be used to disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability of storing data by simultaneously enabling OEAB and OEBA\. Each output reinforces its input in this configuration. When both OEAB and OEBA\ are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 total) remain at their last states.

To ensure the high-impedance state during power up or power down, OEBA\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN54ABT623A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT623 is characterized for operation from -40°C to 85°C.

Products containing the "SN74ABT623" keyword are: SN74ABT623DBR , SN74ABT623DBR , SN74ABT623DBR AB623 , SN74ABT623DW , SN74ABT623DW , SN74ABT623DWR , SN74ABT623DWR , SN74ABT623DWRG4 , SN74ABT623N , SN74ABT623N , SN74ABT623NS , SN74ABT623NSR , SN74ABT623NSR , SN74ABT623NSRE4 , SN74ABT623NSRG4 , SN74ABT623NSRG4 , SN74ABT623PW , SN74ABT623PW , SN74ABT623PWE4 , SN74ABT623PWG4

• State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Typical V_OLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25°C
• High-Drive Outputs (-32-mA I_OH, 64-mA I_OL)
• Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (N) and Ceramic (JT) DIPs

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