The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
Products containing the "ADC34J43" keyword are: ADC34J43EVM , ADC34J43EVM , ADC34J43IRGZ25 , ADC34J43IRGZ25 , ADC34J43IRGZR , ADC34J43IRGZR , ADC34J43IRGZT , ADC34J43IRGZT| Status | ACTIVE |
| SubFamily | High-speed ADCs (>10MSPS) |
| Resolution | 14 |
| Sample Rate | 80 |
| Number of input channels | 4 |
| INL | |
| SNR | 73.1 |
| SFDR | 95 |
| Power consumption | 584 |
| Interface | JESD204B |
| Architecture | Pipeline |
| Operating temperature range | -40 to 85 |
| Rating | Catalog |
| Package Group | VQFN|48 |
| Package size: mm2:W x L (PKG) | [pf]48VQFN[/pf]: 49 mm2: 7 x 7 (VQFN|48) |
| Approx. price | 44.10 | 1ku |
| Analog input BW | 450 |