This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, CLKBA, and CLKENBA\.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16601 is characterized for operation from 40°C to 85°C.Products containing the "SN74ALVCH16601" keyword are: SN74ALVCH16601DGGR , SN74ALVCH16601DGVR , SN74ALVCH16601DL , SN74ALVCH16601DLR
Widebus, UBT, EPIC are trademarks of Texas Instruments.
|SubFamily||Universal bus transceiver (UBT)|
|Package size: mm2:W x L (PKG)||[pf]56SSOP[/pf]: 191 mm2: 10.35 x 18.42 (SSOP|56)|
|Approx. price||0.82 | 1ku|