This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN\ inputs are low. The select (SEL)\ line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA\ inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). The control terminals are registered to synchronize the bus-direction changes with CLK.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from 40°C to 85°C.
Products containing the "SN74ALVCH16270" keyword are: SN74ALVCH16270DGGR , SN74ALVCH16270DGGR T , SN74ALVCH16270DL , SN74ALVCH16270DL , SN74ALVCH16270DLR , SN74ALVCH16270DLRWidebus, EPIC are trademarks of Texas Instruments.
Status | ACTIVE |
SubFamily | Universal bus exchanger (UBE) |
Technology Family | ALVC |
Rating | Catalog |
Package Group | SSOP|56 |
Package size: mm2:W x L (PKG) | [pf]56SSOP[/pf]: 191 mm2: 10.35 x 18.42 (SSOP|56) |
Approx. price | 0.82 | 1ku |