SN74ALVC162334 - 16-Bit Universal Bus Driver With 3-State Outputs

This 16-bit universal bus driver is designed for 1.65-V to 3.6-V V_CC operation.

Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Products containing the "SN74ALVC162334" keyword are: SN74ALVC162334DGG , SN74ALVC162334DGGE4 , SN74ALVC162334DGGR , SN74ALVC162334DGGR , SN74ALVC162334DGGRG4 , SN74ALVC162334DGVR , SN74ALVC162334DGVR T/REE , SN74ALVC162334DGVRG4 , SN74ALVC162334DL , SN74ALVC162334DLG4 , SN74ALVC162334DLR , SN74ALVC162334DLR

• Member of the Texas Instruments Widebus™ Family
• Ideal for Use in PC100 Register DIMM
• Operates From 1.65 V to 3.6 V
• Max t_pd of 3.8 ns at 3.3 V
• ±12-mA Output Drive at 3.3 V
• Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
• Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments.