The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked loop (PLL) circuit that contains a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear operational amplifier techniques. Various applications include telecommunications, digital phase-locked loop and signal generators.
Products containing the "SN74LV4046A" keyword are: SN74LV4046AD , SN74LV4046AD , SN74LV4046ADG4 , SN74LV4046ADG4 , SN74LV4046ADGVR , SN74LV4046ADGVR , SN74LV4046ADR , SN74LV4046ADR , SN74LV4046ADRG4 , SN74LV4046ADRG4 , SN74LV4046AN , SN74LV4046AN , SN74LV4046ANE4 , SN74LV4046ANE4 , SN74LV4046ANS , SN74LV4046ANS , SN74LV4046ANSR , SN74LV4046ANSR , SN74LV4046ANSRG4 , SN74LV4046APWStatus | ACTIVE |
SubFamily | Phase-locked-loop (PLL)/oscillator |
Technology Family | LV-A |
VCC | 5.5 |
Bits | 1 |
Voltage | 5 |
F @ nom voltage | 70 |
ICC @ nom voltage | 0.05 |
tpd @ Nom Voltage | 60 |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | PDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.47 | 1ku |