CD74HC138-Q1 - Automotive Catalog High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer Inverting and Non-Invert

The CD74HC138 is a high-speed silicon-gate CMOS decoder well suited to memory address decoding or data routing applications. This circuit features low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low-power Schottky TTL logic. The circuit has three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 will go low.

Two active-low and one active-high enables (E1, E2, and E3) are provided to ease the cascading of decoders. The decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads.

• Qualified for Automotive Applications
• Select One of Eight Data Outputs Active Low
• I/O Port or Memory Selector
• Three Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13 ns at V_CC = 5 V, C_L = 15 pF, T_A = 25°C
• Fanout (Over Temperature Range)
  • Standard Outputs . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . 15 LSTTL Loads
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• 2-V to 6-V V_CC Operation
• High Noise Immunity; N_IL or N_IH = 30% of V_CC, V_CC = 5 V