CD4532B consists of combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned priority; D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip-enable input EI is low. When EI is high, the binary representation of the highest-priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable-out (EO) is high when no priority inputs are present. If any one input is high, EO is low and all cascaded lower-order stages are disabled.
The CD4532B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Products containing the "CD4532B" keyword are: CD4532BE , CD4532BE , CD4532BE-NG , CD4532BE. , CD4532BEE4 , CD4532BEE4 , CD4532BEG4 , CD4532BEX , CD4532BF , CD4532BF/3 , CD4532BF/3A , CD4532BF3A , CD4532BFX , CD4532BM , CD4532BM , CD4532BM96 , CD4532BM96 , CD4532BM96E4 , CD4532BM96E4 , CD4532BM96G4Data sheet acquired from Harris Semiconductor
Status | ACTIVE |
SubFamily | Encoders & decoders |
Technology Family | CD4000 |
VCC | 18 |
Bits | 8 |
Voltage | 5^10^15 |
F @ nom voltage | 8 |
ICC @ nom voltage | 0.3 |
tpd @ Nom Voltage | 110 |
Rating | Catalog |
Operating temperature range | -55 to 125 |
Package Group | PDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.12 | 1ku |