These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ´273 and 10 milliwatts for the ´LS273.
Products containing the "SN74LS273" keyword are: SN74LS273DW , SN74LS273DW , SN74LS273DWG4 , SN74LS273DWR , SN74LS273DWR , SN74LS273DWR(PB-FREE) , SN74LS273DWR2 , SN74LS273DWRG4 , SN74LS273H , SN74LS273J , SN74LS273MEL , SN74LS273ML1 , SN74LS273N , SN74LS273N , SN74LS273NE4 , SN74LS273NE4 , SN74LS273NG4 , SN74LS273NS , SN74LS273NSLE , SN74LS273NSR
Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | LS |
VCC | 5.25 |
Bits | 8 |
Voltage | 5 |
F @ nom voltage | 35 |
ICC @ nom voltage | 27 |
tpd @ Nom Voltage | 27 |
3-state output | No |
Rating | Catalog |
Operating temperature range | 0 to 70 |
Package Group | PDIP|20 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.30 | 1ku |