These 8-bit shift registers feature gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup-time requirements will be entered. Clocking occurs on the low-to-high-level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.
The SN54164 and SN54LS164 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74164 and SN74LS164 are characterized for operation from 0°C to 70°C.
Products containing the "SN74LS164" keyword are: SN74LS164D , SN74LS164D , SN74LS164DB , SN74LS164DE4 , SN74LS164DG4 , SN74LS164DR , SN74LS164DR , SN74LS164DR2 , SN74LS164DRE4 , SN74LS164DRE4 , SN74LS164DRG4 , SN74LS164MEL , SN74LS164N , SN74LS164N , SN74LS164N/MB74LS164 , SN74LS164N/SN74LS164N , SN74LS164N3 , SN74LS164NE4 , SN74LS164NE4 , SN74LS164NG4
| Status | ACTIVE |
| SubFamily | Shift register |
| Technology Family | LS |
| VCC | 5.25 |
| Bits | 8 |
| Voltage | 5 |
| F @ nom voltage | 35 |
| ICC @ nom voltage | 27 |
| tpd @ Nom Voltage | 32 |
| 3-state output | No |
| Rating | Catalog |
| Operating temperature range | 0 to 70 |
| Package Group | PDIP|14 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.22 | 1ku |