These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the '175, 'LS175, and 'S175 feature complementary outputs from each flip-flop.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Products containing the "SN74LS175" keyword are: SN74LS175D , SN74LS175D , SN74LS175DG4 , SN74LS175DG4 , SN74LS175DR , SN74LS175DR , SN74LS175DR2 , SN74LS175DRG4 , SN74LS175MEL , SN74LS175MR1 , SN74LS175N , SN74LS175N , SN74LS175N-K , SN74LS175N3 , SN74LS175ND , SN74LS175NDS , SN74LS175NE4 , SN74LS175NE4 , SN74LS175NG4 , SN74LS175NSStatus | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | LS |
VCC | 5.25 |
Bits | 4 |
Voltage | 5 |
F @ nom voltage | 35 |
ICC @ nom voltage | 18 |
tpd @ Nom Voltage | 25 |
3-state output | No |
Rating | Catalog |
Operating temperature range | 0 to 70 |
Package Group | PDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.26 | 1ku |