SN74AS74A - Dual Positive-Edge-Triggered D-Type Flip-Flops With Preset And Clear
Updated : 2020-01-09 14:40:36These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
Products containing the "SN74AS74A" keyword are: SN74AS74AD , SN74AS74AD , SN74AS74ADB , SN74AS74ADB(AS74A) , SN74AS74ADB/AS74A , SN74AS74ADBLE , SN74AS74ADBR , SN74AS74ADR , SN74AS74ADR , SN74AS74ADRG4 , SN74AS74AN , SN74AS74AN , SN74AS74ANG4 , SN74AS74ANS , SN74AS74ANSE4 , SN74AS74ANSR , SN74AS74ANSR , SN74AS74ANSRG4 , SN74AS74ANSRG4 (RE-REEL)
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
| Status | ACTIVE |
| SubFamily | D-type flip-flop |
| Technology Family | AS |
| VCC | 5.5 |
| Bits | 2 |
| Voltage | 5 |
| F @ nom voltage | 125 |
| ICC @ nom voltage | 16 |
| tpd @ Nom Voltage | 9 |
| 3-state output | No |
| Rating | Catalog |
| Operating temperature range | 0 to 70 |
| Package Group | PDIP|14 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.45 | 1ku |
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