These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs regardless of the levels of the other inputs. When
and
are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C.
Products containing the "SN74ALS109A" keyword are: SN74ALS109AD , SN74ALS109AD , SN74ALS109ADG4 , SN74ALS109ADG4 , SN74ALS109ADR , SN74ALS109ADR , SN74ALS109AN , SN74ALS109AN , SN74ALS109ANE4 , SN74ALS109ANG4 , SN74ALS109ANS , SN74ALS109ANS-L1 , SN74ALS109ANSG4 , SN74ALS109ANSR , SN74ALS109ANSR
| Status | ACTIVE |
| SubFamily | J-K flip-flop |
| Technology Family | ALS |
| VCC | 5.5 |
| Bits | 2 |
| Voltage | 5 |
| F @ nom voltage | 75 |
| ICC @ nom voltage | 4 |
| tpd @ Nom Voltage | 15 |
| 3-state output | |
| Rating | Catalog |
| Operating temperature range | 0 to 70 |
| Package Group | PDIP|16 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.48 | 1ku |